Abstracts

Title: Explorations in Parallelism
Presenter: Ravi Rajwar
Abstract: The slowing growth in single-thread performance has meant an increasingly parallel future - involving parallelism across data, threads, cores, and nodes. This future has led to a renewed interest in various aspects of parallelism, including synchronization and transactional memory. This talk explores this resurgence, the growing interplay between hardware and software, and looks ahead at the challenges and opportunities.

Title: Using hardware transactional memory to build resilient systems
Presenter: Christof Fetzer
Abstract: In recent years, there has been an increasing interest in resilient computing. It is expected that not only the rate of single event upsets will increase, but that we will experience accelerated aging and an increase in transistor variability. This will result in an increasing rate of transient and permanent errors. In our research, we investigate the use of hardware transactional as a mechanism to help  to mask transient errors and to cope with permanent errors. In my presentation, I will given an introduction to the problem, present our approach and our initial results.

Title: Commercial-Off-the-shelf Hardware Transactional Memory for Tolerating Transient Hardware Errors
Presenter: Rasha Faqeh 
Abstract: The trend in the modern CMOS technologies is to downscale feature sizes, reduce noise margins and lower voltage levels to increase performance and reduce power consumption. While the trend increases the overall-performance, micro-processor susceptibility to transient faults also increased dramatically. The non-negligible current and future transient fault rates will entail the use of fault tolerance techniques in general purpose systems. General purpose systems (in comparison to safety critical application) is concerned with minimizing the average execution time while applying the fault tolerance. Therefore, to disperse the application of fault tolerance in general purpose systems, low cost and low overhead error detection and recovery mechanisms are needed. 
In this study we want to investigate to what extent transient fault recovery can be implemented leveraging the abort mechanism of commodity hardware transactional memory (HTM) (i.e. Intel TSX, IBM power8) when combined with off-the-shelf software implemented transient error detection (i.e. SWIFT).

Title: A programmer's view of Transactional Memory consistency
Presenter: Hagit Attiya
Abstract: Several definitions has been suggested for the consistency of Transactional Memory (TM) and it is not obvious which of them is the right one to use. This talk addresses the question by taking the programmer's view.
Specifically, a TM consistency condition must preserve  the *observations* a program may obtain when interacting with a TM.
By making this concept precise, we are able to evaluate whether a TM consistency condition is *sufficient* for preserving observations, and which condition is *necessary* for doing so.
Interestingly, we show that the answer depends on program properties:  If local variables are not rolled back when a transaction aborts, then opacity is necessary and sufficient, but when they are, Transactional Memory Specification (TMS1) is necessary and sufficient.
This is joint work with Sandeep Hans, Alexey Gotsman, and Noam Rinetzky.

Title: Gray box performance modelling of distributed TM
Presenter: Diego Didona
Abstract: Classical approaches to performance prediction of applications rely on two, typically antithetic, techniques: Machine Learning (ML) and Analytical Modeling (AM). 
ML undertakes a black-box approach, whose prediction accuracy strongly depends on the representativeness of the data set employed during the initial training phase of the learner.
Conversely, AM relies on a white-box approach, which requires no or minimal training, but whose accuracy can be hindered by the need for introducing simplifying assumptions in order to ensure the model tractability.
In this talk I will present some gray box modelling techniques, which exploit AM and ML in synergy, and apply them to a class of systems whose modelling encompasses a number of harsh challenges: Distributed Transactional Memory (DTM). The investigation of one of the presented techniques has been initiated in conjunction with Pascal Felber’s research team, during my STSM at Unversité de Neuchâtel, and it has been pushed further in subsequent research work, which constitute the backbone of my PhD thesis.

Title: Energy-efficient Transactional Memory
Presenter: Osman Unsal
Abstract: In this talk, I will present a short overview of various approaches to make transactional memory implementations more energy-efficient. Then, I will detail how the versioning and abort mechanisms of transactional memory could be utilized to provide speculative execution below the safe operating voltage in order to save power and energy for general purpose systems.

Title: Transactional Memory for C++: Standardization efforts and commercial implementations
Presenter: Torvald Riegel
Abstract: In this talk, I will give an overview of (1) the current state of the standardization efforts around C++ Transactional Memory constructs by the ISO C++ committee, and (2) support for these constructs in commercial implementations such as the GNU Compiler Collection.