Transactional Memories: Foundations, Algorithms, Tools, and Applications

Participant: Prof. Dimiter Avresky

Home Institution:
IRIANC

Home Country: Germany

Host: Prof. Bruno Ciciani

Host Institution: Sapienza Universita’ di Roma
 
Host Country: Italy

Start Date:
2012-11-06

End Date: 2012-12-06

Description:
The purpose of this STSM is to study and develop a Scalable Protocol, based on Partially Replicated Transactional Systems and Resilient Transport Layer in large multicore chips (beyond 1000 cores ), for seamless execution of NonDAG graph parallel applications in the presence of multiple failures.

Report: here