A Hardware Approach for Detecting, Tolerating and Exposing High Level Atomicity Violations

Participant: Lois Orosa

Home Institution: 
University of Santiago de Compostela

Home Country: Spain

Host: Prof. João Lourenço

Host Institution: FCT, Universidade Nova de Lisboa 
Host Country: Portugal

Start Date:

End Date: 2013-12-30

The purpose of this short term scientific mission (STSM) was to design a tool that would tolerate atomicity violations in a transactional memory system implementing weak isolation. In these TM systems, the conflict detection mechanism only detects conflicts between transactions, but not between transactional and non-transactional accesses. We consider the accesses to shared data not enclosed in a transaction as bugs (asymmetric data races, or transactional atomicity violations). From this point of view, we want to build a tool to detect and tolerate these bugs in a weak isolation TM system by prioritizing transactions over the buggy threads.
After some research on this topic, we decided to change it because we didn’t find potential enough for making a significant scientific contribution. Instead, we decide to explore High-Level Atomicity Violations (HLAV) in concurrent programs, a topic that has not yet been addressed in a hardware approach. HLAV result from the misspecification of the scope of an atomic block, by splitting it in two or more atomic blocks which may be interleaved with other atomic blocks. In this work we address a solution for detecting, exposing and tolerating this type of bugs.

Report: here