Enhancing an HTM system (TMbox) with HW monitoring capabilities

Participant: Philipp Kirchhofer

Home Institution:
Institute of Computer Science & Engineering / Karlsruhe Institute of Technology

Home Country: Germany

Host: Dr. Osman Unsal

Host Institution: Barcelona Supercomputing Center - Microsoft Research Center

Host Country: Spain

Start Date:
2011-06-20

End Date: 2011-09-19

Description:
Transactional Memory (TM) is supposed to simplify parallel programming. Recent research shows that current state-of-the-art TM implementations are on a good way to achieve this goal. Previous work shows that programming with TM semantics exhibits a much smaller error rate compared to programming with traditional fine-grained explicit locking.
But another issue remains: Performance and scalability are both important for a successful adoption of TM. The 90/10 law, originating from software engineering, states that about 90% of application runtime is spent in 10% of code. It is, according to this law, important to know which bottlenecks exist in a given environment to allow the development of scalable and fast applications.
However, in current HTM systems the programmer is often unaware of the application’s behavior which makes the optimization a trial-and-error process. As a consequence the TM applications do not run as efficiently as possible. In STM systems generating event logs at run time or profiling on a per-atomic block level are methods that capture and preserve the dependencies between transactions. Typically these techniques come with software overhead and may influence the application runtime characteristics.
The purpose of this short term scientific mission (STSM) was to address these shortcomings and develop a monitoring infrastructure for an HTM system. This will allow the programmer to get insights into the interaction between application and HTM system, to detect bottlenecks during analysis and to optimize the application for the underlying system. Furthermore the knowledge gained can help to develop new designs leading to faster and more efficient HTM systems. The key design aspects include multi-core-scalability, high extensibility, zero runtime overhead and no influence on application runtime characteristics. The system should also be easily usable by an application developer.

Report: here