WG Leader: Prof. Gilles Muller
Albeit TMs can be purely implemented in software, there is a growing consensus that some form of hardware support is desirable to improve performance.
By providing hardware level support for conflict detection and version management, in fact, the bookkeeping overhead incurred by STMs can be drastically reduced, making TMs' performance superior even to that of hand-crafted, fine grain, locking. On the other hand, the implementation of these mechanisms in hardware is way more problematic than in software, as this can entail invasive, risky modifications of crucial components of existing processors such as cache, TLB and bus protocol.
An alternative solution, that appears more viable in the near future, is to rely on hybrid approaches that require simpler (and therefore less disruptive) best-effort hardware mechanisms, capable of boosting transactions in common execution scenarios, and to resort to software implementations only whether needed. The researchers participating in this WG will explore the design space of hardware supports (hybrid and not) for TMs, and investigate the relations between hardware, operating system and user level applications. This includes: understanding if, or at what extent, modern OSs can take advantage of various TM hardware supports (e.g., for synchronizations within the kernel) to enhance their performance and/or reliability; evaluating pros and cons of the integration of TM APIs at the OS level; devising efficient OS level mechanisms allowing TMs' transactions to encompass interactions with hardware devices and/or system call invocations, one of the major limitations of current TM systems.
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